• Ph.D. in Computer Engineering, Sharif University of Technology, Tehran, Iran (March 2007)
• M.Sc. in Computer Engineering, Sharif University of Technology, Tehran, Iran (September 2002)
• B.Sc. in Computer Engineering, Sharif University of Technology, Tehran, Iran (September 2000)

• Research Visitor, Bristol University, UK, Dhiraj K. Paradhan (June 2006-Nov.2006)
• Amirkabir University of Technology:
    -Reliable System Design (MS)
    -Advanced Topics in Dependable Computer System Design (MS)
    -Machine Language and System Programming (BS)
    -Computer Architecture (BS)
• Sharif University of Technology:
    -Computer Architecture (BS)
    -Microprocessor Lab (BS)

• IEEE Member
• Computer Society of IRAN (CSI) member

DADS Laboratory:
http://ceit.aut.ac.ir/dads/

• N. Khoshavi, H.R. Zarandi, M. Maghsoudloo, "Two Control-flow Error Recovery Methods for Multithreaded Programs Running on Multi-core Processors,” 28th International Conference on Microelectronics, May, 2012.
• M. Maghsoudloo, H.R. Zarandi, N. Khoshavi, “A Low-Cost Software-Implemented Error Detection Technique,” International Symposium on Electronic System Design (ISED), Kochi, India, Dec. 2011.
• H. Aliee, H.R. Zarandi, “A Fault-Tolerant, Dynamically Scheduled Pipeline Structure for Chip Multiprocessors,” 30th International Conference on Computer Safety, Reliability and Security (SAFECOMP), Naples, Italy, Sep. 19-20, 2011.
• M. Raji, B. Ghavami, H.R. Zarandi, H. Pedram, “Assessment of Nano-scale Asynchronous PCFB Circuits under Extreme Process Variation,” Asia Symposium on Quality Electronic Design (ASQED), Malaysia, July 19-20, 2011.
• R. Salamat, H.R. Zarandi, “Fault-Tolerance Assessment and Enhancement in SoCWire Interface: A System-On-Chip Wire,” IEEE International On-Line Testing Symposium (IOLTS), Greece, July 13-15, 2011.
• N. Khoshavi, H.R. Zarandi, M. Maghsoudloo, “Control-Flow Error Recovery Using Commodity Multi-core Architecture Features,” IEEE International On-Line Testing Symposium (IOLTS), Greece, July 13-15, 2011.
• M. Maghsoudloo, S. Pour-Mozaffari, H.R. Zarandi, N. Khoshavi, “Soft Error Detection Technique in Multi-threaded Architectures Using Control-Flow Monitoring,” 14th Euromicro Conference on Digital System Design, Architecture, Methods and Tools (DSD), Oulu, Finland, August 31-Sep. 2, 2011.
• H. Aliee, H.R. Zarandi, A. Tajary, “CPU-Aware, Process-Level Redundancy to Tolerate Faults in Multi-cores,” in 9th IEEE International Conference on High Performance Computing & Simulation (HPCS), Istanbul, Turkey, July 4-8, 2011.
• N. Khoshavi, H.R. Zarandi, M. Maghsoudloo, “Control-Flow Error Detection Using Combining Basic and Program-Level Checking in Commodity Multi-core Architectures,” Symposium on Industrial Embedded Systems (SIES), Vasteras, Sweden, June 15-17, 2011.
• H. Aliee, H.R. Zarandi, “An Efficient, Dynamically Adaptive Method to Tolerate Transient Faults in Multi-core Systems,” accepted to appear in 13th European Workshop on Dependable Computing (EWDC), Pisa, Italy, 11-12 May, 2011.
• H.R. Zarandi, N. Khoshavi, M. Maghsoudloo, "Two Efficient Software Techniques to Detect and Correct Control-flow Errors," accepted to appear in The 16th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC), Tokyo, Japan, 2010.
• M. Zandrahimi, H.R. Zarandi, A. Zarei, "A Probabilistic Method to Detect Anomalies in Embedded Systems," accepted to appear in 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), Kyoto, Japan, 2010.
• H. Aliee, H.R. Zarandi, "Fault Tree Analysis Using Stochastic Logic: A Reliable and High Speed Method," accepted in 57th Annual Reliability & Maintainability Symposium (RAMS), Orlando, 2011.
• M. Zand-Rahimi, H.R. Zarandi, A. Zarei, “A Cache-based Anomaly Detector for Embedded Systems,” Annual International Conference on Real-Time and Embedded Systems (RTES), 1 – 2 November 2010, Singapore.
• M. Raji, A. Tajari, B. Ghavami, H. Pedram, H.R. Zarandi, "Statistical Leakage Power Optimization of Asynchronous Circuits Considering Process Variations," 19th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), September, France, 2010
• M. Zandrahimi, H.R. Zarandi, A. Rohani, "An Analysis of Fault Effects and Propagations in ZPU: The World's Smallest 32 bit CPU," the Asia Symposium on Quality Electronic Design (ASQED), Malaysia, 2010.
• H. Aliee, H.R. Zarandi, "A Quad Router Design for Next Generation CMPs," to appear in 15th CSI International Symposium on Computer Architecture and Digital Systems (CADS), Tehran, September, 2010.
• M. Maghsoudloo, N. Khoshavi, H.R. Zarandi, "CCDA: Correcting Control-Flow and Data Errors Automatically," to appear in 15th CSI International Symposium on Computer Architecture and Digital Systems (CADS), Tehran, September, 2010.
• S. Khoshbakht, H.R. Zarandi, "Analysis of Soft Error Effects on CAN Network Controller," to appear in 15th CSI International Symposium on Computer Architecture and Digital Systems (CADS), Tehran, September, 2010.
• M. Didehban, S. Khoshbakht, H.R. Zarandi, S. Pourmozaffari, "Reduction of Soft Error Effects on MIPS-based Dual Core," to appear in 15th CSI International Symposium on Computer Architecture and Digital Systems (CADS), Tehran, September, 2010.
• F. Mohammadian, A. Eghbal, S. Pourmozafari, H.R. Zarandi, "SET and SEU Effects on a PLASMA Processor Assessment," to appear in 15th CSI International Symposium on Computer Architecture and Digital Systems (CADS), Tehran, September, 2010.
• S. Khoshbakht, H.R. Zarandi, "Soft Error Propagation and Effects Analysis on CAN Controller," IEEE International Conference on Automation, Quality and Testing, Robotics (AQTR), 2010.
• S. Bahramnejad, H.R. Zarandi, M. Shojaei, "Investigation of Transient Faults on JOP Processor,"IEEE International Conference on Automation, Quality and Testing, Robotics (AQTR), Tehran, September, 2010.
• H. Aliee, H.R. Zarandi, "NOTIFY: a Network-On-chip-based Tool to Inject Faults extensively," to appear in IEEE Latin American Symposium on Circuits and Systems (LASCAS), Brazil, Feb. 2010.
• S. Bahramnejad, H.R. Zarandi, "An Adaptive Redundancy Oriented Method to Tolerate Soft Errors in SRAM-based FPGAs Using Unused Resources," the International Conference on Availability, Reliability and Security (ARES), Poland, Feb. 15-18, 2010.
• I. Faraji, M. Didehban, H.R. Zarandi, "Analysis of Transient faults on a MIPS-based Dual-Core Processor," the International Conference on Availability, Reliability and Security (ARES), Poland, Feb. 15-18, 2010.
• A. Rohani, H.R. Zarandi, "A New CLB Architecture for Tolerating SEU in SRAM-based FPGAs," International Conference on ReConfigurable Computing and FPGAs (Reconfig), Mexico, 2009.
• A. Rohani, H.R. Zarandi, "New Switch Box Architecture for SEU Detection in SRAM-based FPGAs," International Conference on Computer Science and Its Applications (CSA), Korea, 2009.
• S. Bahramnejad, H.R. Zarandi, "A SEU-Avoidance Method in Placement and Routing of SRAM-based FPGAs to Mitigate Soft Error Effects," International Workshop on Design for Reliability and Variability (DRVW), USA, 2009.
• P. Yaghini, A. Eghbal, H. Pedram, H.R. Zarandi, "Investigation of Transient Fault Effects in an Asynchronous NOC Router," the 18th Euromicro International Conference on Parallel, Distributed and Network-based Computing (PDP), Italy, 2010.
• H. Ebrahimi, M. Saheb-Zamani, H.R. Zarandi, "A Decoder-based Switch Box to Mitigate Soft Errors in SRAM-based FPGAs,"15th Asia and South Pacific Design Automation Conference (ASPDAC), Taiwan, 2010.
• S. Bahramnejad, H.R. Zarandi, "A Fault-Tolerant Combined Method for SRAM-based FPGAs," 10th IEEE Workshop on RTL and High Level Testing (WRTLT), Hong Kong, Nov. 27-28, 2009.
• B. Ghavami, M. Zamani, H.R. Zarandi, "High-Level Fault Simulation Methodology for QDI Template-Based Asynchronous Circuits", IEEE TENCON International Conference, Singapore, November 23-26, 2009.
• H. Sadeghi, H. Sarbazi-Azad, H.R. Zarandi, "Power-Aware Branch Target Prediction Using a New BTB Architecture", 17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSISOC), Brazil, October 12-14, 2009.
• B. Ghavami, H. R. Zarandi, H. Pedram, "Testing and Diagnosis of Faults in Template-Based Asynchronous Circuits," International Symposium on SoC (SOC), Finland, October 5-6, 2009.
• S. A. Asghari, M. Khademi, M. Ansarinia, Hamid R. Zarandi, H. Pedram, "An Innovative Fault Injection Method in Embedded Systems via Background Debug Mode," 14th International CSI Computer Conference (CSICC), Tehran, Iran, 2009.
• M. Raji, B. Ghavami, H.R. Zarandi, H. Pedram, "Process Variation Aware Performance Analysis of Asynchronous Circuits Considering Spatial Correlation," 19th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Netherlands, September 9-11, 2009.
• A. Rohani, H.R. Zarandi, "Mitigating and Tolerating SEU Effects in Switch Modules of SRAM-based FPGAs", in the V IEEE Southern Programmable Logic Conference (SPL), Brazil, April 1-3, 2009.
• A. Eghbal, P.M. Yaghini, H. Pedram, H.R. Zarandi, "Fault Tolerance Evaluation of a Synchronous NoC Router Based on Fault Injection," in the IEEE International On-Line Testing Symposium (IOLTS), Sesimbra-Lisbon, Portugal, June 2009.
• S. A. Asghari, Hamid R. Zarandi, Mohammad Khademi, Morteza Ansari, "A Fault Injection Attitude based on Background Debug Mode in Embedded Systems," in the International Conference on Computer Design (CDES), July 2009.
• P.M. Yaghini, H.R. Zarandi, A. Eghbal, "An Investigation of Fault Tolerance Behavior of 32-bit DLX Processor," The Second International Conference on Dependability (DEPEND), 2009.
• A. Eghbal, H.R. Zarandi, P. Yaghini "Fault Tolerance Assessment of PIC Microcontroller Based on Fault Injection," in the 10th IEEE Latin-American Test Workshop (LATW), Brazil, 2009.
• A. Rohani, H.R. Zarandi, "An Analysis of Fault Effects and Propagations in the AVR Microcontroller ATmega103(L)," in the 4th International Conference on Availability, Reliability and Security (ARES), IEEE Press, Japan, 2009.
• C. Argyrides, H.R. Zarandi, D. K. Pradhan, “Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories,” to appear in the 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), Italy, 2007.
• H. R. Zarandi, S.G. Miremadi, C. Argyrides, D. K. Pradhan, “Multiple SEU Tolerance in LUTs of FPGAs Using Protected Schemes,” in the Proceedings of 12th IEEE European Test Symposium (ETS), Germany, 2007.
• C. Argyrides, D. K. Pradhan, H. R. Zarandi, “An Efficient Method to Tolerate Multiple Bit Upsets in SRAM Memory,” in the Proceedings of 12th IEEE European Test Symposium (ETS), Germany, 2007.
• H. R. Zarandi, S. G. Miremadi, D. K. Pradhan, J. Mathew, “Soft Error Mitigation in Switch Modules of SRAM-based FPGAs,” in the Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), New Orleans, USA, 27-30 May, 2007.
• H. R. Zarandi, S. G. Miremadi, D. K. Pradhan, J. Mathew, “CAD-Directed SEU Susceptibility Reduction in FPGA Circuit Designs,” in the Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), New Orleans, USA, 27-30 May, 2007.
• H. R. Zarandi, S. G. Miremadi, D. K. Pradhan, C. Argyrides, “Online Detection and Correction of Soft-Errors in LUTs of SRAM-based FPGAs,” in the Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), New Orleans, USA, 27-30 May, 2007.
• H. R. Zarandi, S. G. Miremadi, D. K. Pradhan, C. Argyrides, “Exploiting Unused Routing Resources of Switch Modules to Tolerate SEUs in SRAM-based FPGAs,” in the Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), New Orleans, USA, 27-30 May, 2007.
• H. R. Zarandi, S. G. Miremadi, D. K. Pradhan, J. Mathew, "SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-based FPGAs," in Proceeding of IEEE International Symposium on Quality Electronic Design (ISQED 2007), San Jose, CA, 2007.
• H. R. Zarandi, S. G. Miremadi, D. K. Pradhan, C. Argyrides, “Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs,” in the proceedings of 14th IEEE Reconfigurable Architecture Workshop, in associated with IPDPS, California, USA, 2007.
• A. Bakhoda, S. G. Miremadi, H. R. Zarandi, "Investigation of Transient Effects on FPGA-based Embedded Systems," in Proceeding of Second International Conference on Embedded Software and Systems (ICESS 2006), IEEE-CS Press, Xian, China, Dec. 16-18, 2005.
• A. Bakhoda, S. G. Miremadi, H. R. Zarandi, "Experimental Evaluation of Transient Effects on SRAM-based FPGA Chips," in Proceeding of 17th IEEE International Conference on Microelectronics (ICM 2006), Islamabad, Pakistan, Dec. 13 to 15, 2005.
• H. R. Zarandi, S. G. Miremadi, “Soft Error Mitigation in Cache Memories of Embedded Systems By Means of a Protected Scheme,” in the Proceedings of Latin-American Symposium on Dependable Computing (LADC 2005), Lecture Notes in Computer Science (LNCS), Salvador-Bahia, Brazil, October 2005.
• H. R. Zarandi, S. G. Miremadi, “Hierarchical Multiple Associative Mapping in Cache Memories,” in the Proceedings of 12th IEEE International Conference on Engineering of Computer Based Systems (ECBS), Maryland, USA, April 2005.
• S. G. Miremadi, H. R. Zarandi, “Reliability of Protecting Techniques Used in Fault-Tolerant Cache Memories,” to appear in the Proceedings of 18th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE), Saskatoon, Canada, 2005.
• H. R. Zarandi, S. G. Miremadi, “Fault Tree Analysis of Embedded Systems Using SystemC,” in the Proceedings of the 51st IEEE Annual Reliability and Maintainability Symposium, (RAMS), Alexandria, USA, January 2005.
• H. R. Zarandi, S. G. Miremadi, “A Highly Fault Detectable Cache Architecture For Dependable Computing,” in the 23rd International Conference on Computer Safety, Reliability and Security (SAFECOMP), Lecture Notes in Computer Science (LNCS), Germany, 2004.
• H. R. Zarandi, S. G. Miremadi, H. Sarbazi-Azad, “Fault Detection Enhancement in Cache Memories Using a High Performance Placement Algorithm,” in the IEEE International On-Line Testing Symposium (IOLTS), Madeira Island, Portugal, July 2004.
• H. R. Zarandi, S. G. Miremadi, S. Hessabi, A. Ejlali, "A Mixed-Mode Simulation-Based Environment to Test and Dependability Assessment of HDL Models," in the Proceedings of International Conference on Embedded Systems and Applications (ESA), Las Vegas, Nevada, USA, June, 2004.
• G. Asadi, S. G. Miremadi, H. R. Zarandi, A. Ejlali, "Evaluation of Fault-Tolerant Designs Implemented on SRAM-Based FPGAs," in the Proceedings of the IEEE/IFIP Pacific Rim International Symposium on Dependable Computing (PRDC), Papeete, Tahiti, French Polynesia, 3-5 March, 2004.
• H. R. Zarandi, H. Sarbazi-Azad, "An Efficient Adaptive Fault-Tolerant Routing in Hypercubes in the Presence of Dynamic Faults," in the Proceedings of 9th CSI Computer Conference (CSICC), Sharif University of Technology, 17-19 February, 2004.
• G. Asadi, G. Miremadi, H. R. Zarandi, A. Ejlali, "Fault Injection into SRAM-Based FPGAs for the Analysis of SEU Effects," in the Proceedings of the IEEE International Conference on Field-Programmable Technology (FPT), Tokyo, Japan, December 2003.
• H. R. Zarandi, G. Miremadi, A. R. Ejlali, "Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models," in the Proceedings of 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), Cambridge, MA, U.S.A, November 2003.
• H. R. Zarandi, G. Miremadi, A. R. Ejlali, "Fault Injection into Verilog Models for Dependability Evaluation of Digital Systems," in the Proceedings of the International Symposium on Parallel and Distributed Computing (ISPDC), (Conference Proceedings Was Published by IEEE Press), Slovenia, October 2003.
• A. R. Ejlali and G. Miremadi, H. R. Zarandi, G. Asadi and S. B. Sarmadi, “A Hybrid Fault Injection Approach Based on Simulation and Emulation Co-Operation,” in the Proceedings of IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), San Francisco, CA, USA, June 2003.
• H. R. Zarandi, G. Miremadi and A. R. Ejlali, “SILVER: A Simulation-Based Fault Injection Tool at Switch Level Using Verilog,” in the Proceedings of the SCIS & ISIS 2002 Conference, Tsukuba, Japan, 2002.

• H. R. Zarandi, S. G. Miremadi, “A SEU-Protected Cache Memory Based on Variable Associativity of Sets,” in Elsevier Journal of Reliability Engineering and System Safety, vol. 92, no. 11, November, 2007, pp. 1584-1596.

• H. R. Zarandi, S. G. Miremadi, “Dependability Evaluation of Altera FPGA-based Embedded Systems Subjected to SEUs,” in Elsevier Journal of Microelectronics Reliability, vol. 47, no. 2-3, February-March, 2007, pp. 461-471.

• H. R. Zarandi, S. G. Miremadi, “A Fault-Tolerant Cache Architecture based on Binary Set Partitioning,” in Elsevier Journal of Microelectronics Reliability, vol. 46, no. 1, January, 2006, pp. 86-99.

• H. R. Zarandi, S. G. Miremadi, “Hierarchical Set-Associative Cache for High-Performance and Low-Energy Applications,” in Journal of Computers, Systems and Circuits (JCSC), World-Scientific Publisher, Vol. 15, No. 6, 2006, pp. 861-880.

• H. R. Zarandi, H. Sarbazi-Azad, “Hierarchical Binary Set Partitioning in Cache Memories,” in Journal of Supercomputing, Kluwer Publishing, vol. 31, no. 2, February 2005, pp. 185 - 202.

• A. Rohani, H. R. Zarandi, "Two Effective Methods to Mitigate Soft Error Effects in SRAM-based FPGAs" in Elsevier Journal of Microelectronics Reliability, vol. 50, no. 8, August 2010, pp. 1171-1180.

• M. Raji, B. Ghavami, H. Pedram, H. R. Zarandi, "Process Variation Aware Performance Analysis of Asynchronous Circuits," in Elsevier Journal of Microelectronics, vol. 41, no. 2-3,February-March, 2010, pp. 99-108.

• P. Rajabzadeh, H. Sarbazi-Azad, H.R. Zarandi, E. Khodaie, H. hashemi, M. ould-khaoua, "Performance Modeling of n-Dimensional Meshes," Elsevier Performance Evaluaion Journal, vol. 67, no. 12, December 2010, pp. 1304-1323.

• A. Eghbal, H. Pedram, P. Yaghini, H.R. Zarandi, "Designing a Fault-tolerant NoC Router Architecture Respecting Fault Effects," Special Issue of the International Journal of Electronics, Francis & Taylor on Network-on-Chip, vol. 97, no. 10, October 2010, pp. 1181-1192.

• H. Ebrahimi, S. Saheb-Zamani, H.R. Zarandi, "Mitigating Soft Errors in SRAM-Based FPGAs by Decoding Configuration Bits in Switch Boxes," Elsevier Microelectronics Journal, vo. 42, no. 1, January 2011, pp. 12-20.

• P. Yaghini, H. Pedram, A. Eghbal, H.R. Zarandi, "Investigation of Transient Fault Effects in Synchronous and Asynchronous Network on Chip Router Reliability,” Elsevier Journal of System Architecture, vol. 57, no. 1, January 2011, pp. 61-68.

• S. Baharmnejad, H.R. Zarandi, “Mitigation of Soft Errors in SRAM-based FPGAs Using CAD Tools,” Elsevier Journal of Computers and Electrical Engineering, vol. 37, no. 6, pp. 1019-1031, November, 2011.

• M. Kishani, H.R. Zarandi, H. Pedram, B. Ghavami, A. Tajari, M. Raji, “HVD: Horizontal-Vertical-Diagonal Error Detecting and Correcting Code to Protect against with Soft Errors,” Springer-Verlag Journal of Design Automation for Embedded Systems (DAES), vol. 15, no. 3, pp. 289-310, 2011.

• S. Bahramnejad, H.R. Zarandi, “An Adaptive Method to Tolerate Soft Errors in SRAM-based FPGAs,” Elsevier Scientia Iranica Transaction D-Computer Science & Engineering and Electrical Engineering, vol. 18, no. 6, pp. 1425-1434, 2011.

• M. Zandrahimi, H.R. Zarandi, M.H. Mottaghi, “Two Effective Methods to Detect Anomalies in Embedded Systems,” Elsevier Journal of Microelectronics, vol. 43, no.1, pp. 77-87, 2012.

Email: h<underline>zarandi@aut.ac.ir
Tel: +98 (21) 645 427 02
Fax: +98 (21) 664 955 21